Recognition of logic diagrams by identifying loops and rectilinear polylines

Proposed is a system that recognizes logic symbols and their inter{connections on logic diagrams. Input diagram, digitized by scanner, is converted into a set of line segments through a sequence of picture processing operations. Then symbols and connections are extracted by identifying loops and rectilinear polylines utilizing model{base in which symbols are graphically described. Experiment with a number of logic diagrams shows that the system correctly recognizes more than 96 % of logic symbols and connections on A4-size diagram with an average complexity within 15 seconds on a workstation .